1. Technical Field
The inventive concept relates to a nonvolatile semiconductor memory devices and, more particularly, to a phase change memory device capable of reducing a reset current, a method of manufacturing the same and a circuit of the same.
2. Related Art
Memory devices are classified into a volatile and non-volatile memory devices. Volatile memory devices include random access memory (RAM) devices which lose data stored therein when power is turned off. Non-volatile memory devices include read only memory (ROM) devices which retain stored data therein when power is turned off. Typically, dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices are regarded as RAMs and flash memory devices is regarded as the ROMs.
As is well known, DRAMs consume low amounts of power and provide simple random access. However, DRAMs exhibit a volatile property and require an increase in the capacity of a capacitor due to high charge storage demands. Meanwhile, SRAMs which are used as cache memories provide random access and high operation speeds. However SRAMs exhibit a volatile property as well as high fabrication cost limit their availability and they require a relatively large size. Flash memory devices are also non-volatile. Due to the two-layered stack gate structure, flash memory devices require operation voltages that are higher than their respective power voltages. Accordingly flash memory devices require separate voltage boosting circuits for generating the desired program voltages and erase voltages. As such, flash memory devices are difficult to integrate and they operate at slow speeds.
To address some of the above problems, ferroelectric random access memory (FRAM) devices, a magnetic random access memory (MRAM) devices and a phase change random access memory (PRAM) devices have been investigated as possible alternative storage medium schemes.
Among these new alternative memory devices, PRAMs use phase change materials as storage media which has a higher resistance in an amorphous state than in a more ordered crystalline state. PRAMs promise to provide faster operation speed and higher integrity as compared with the flash memory device. Typically, the phase change material may be a chalcogenide (GST)-based material which performs memory operation depending to the distinctly different solid state phases
As shown in FIG. 1, PRAMs can include heating electrode 10 positioned below a phase change material 20 to induce heating, via a Joule heating phenomenon, of the phase change material so that resistance deformation of the phase change material can be reversibly performed. Since the higher temperature than the melting point of the phase change material should be applied to the phase change material of the PRAM so as drive the phase change transition of the phase change material 20 from a set state (a low resistance state corresponds to an ordered crystalline solid state) to a reset state (a high resistance state corresponds to a disordered amorphous solid state), a relatively high reset current is needed as shown in FIG. 2. According, higher power consumption is needed to achieve an adequate reset current.
Typically, a heating electrode 10 is chosen to be composed of a high resistive material so as to generate a large amount of heat, as well as, to reduce the requisite amount of current needed in the reset operation. That is, the amount of current is reduced in the {circle around (a)} direction in the prior art. However, if the heating electrode 10 is formed of a high resistive material, the resistance of the heating electrode 10 is affected to the effective resistance of the phase change material 20 such that the resistance of the phase change material 20 in a set state is increased ({circle around (b)}). Due to this, the non-ideal sensing margin S2 is shown to be the difference between the set resistance Rs′ and the reset resistance Rr in which S2 is reduced as compared with the ideal sensing margin S1 in an ideal state, and thereby causing error in read of data. The ideal sensing margin S1 is defined as the difference between the ideal set resistance Rs and the reset resistance Rr.